Dajiang Zhou

410 total citations
30 papers, 302 citations indexed

About

Dajiang Zhou is a scholar working on Signal Processing, Computer Vision and Pattern Recognition and Sociology and Political Science. According to data from OpenAlex, Dajiang Zhou has authored 30 papers receiving a total of 302 indexed citations (citations by other indexed papers that have themselves been cited), including 29 papers in Signal Processing, 28 papers in Computer Vision and Pattern Recognition and 6 papers in Sociology and Political Science. Recurrent topics in Dajiang Zhou's work include Video Coding and Compression Technologies (29 papers), Image and Video Quality Assessment (24 papers) and Advanced Data Compression Techniques (13 papers). Dajiang Zhou is often cited by papers focused on Video Coding and Compression Technologies (29 papers), Image and Video Quality Assessment (24 papers) and Advanced Data Compression Techniques (13 papers). Dajiang Zhou collaborates with scholars based in Japan and China. Dajiang Zhou's co-authors include Jinjia Zhou, Satoshi Goto, Jiayi Zhu, Fei Wei, Peilin Liu, Gang He, Xun He, Satoshi Goto, Takeshi Yoshimura and Heming Sun and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems for Video Technology and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Dajiang Zhou

28 papers receiving 295 citations

Peers

Dajiang Zhou

CVPR

EEE

CNC

Daniel Palomino Brazil

Cyril Bergeron France

Zhenyu Liu China

Dan Grois Israel

Kenneth Andersson Sweden

Chun-Fu Shen Taiwan

Adarsh K. Ramasubramonian United States

Valeri George Germany

A. Puri United States

V. Seferidis United Kingdom

Daniel Palomino Brazil

Dajiang Zhou

360 ×1.3

CVPR

356 ×1.4

56 ×1.3

EEE

21 ×0.6

CNC

9 ×0.5

Citations per year, relative to Dajiang Zhou Dajiang Zhou (= 1×) peers Daniel Palomino

Countries citing papers authored by Dajiang Zhou

Since Specialization

Citations

This map shows the geographic impact of Dajiang Zhou's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Dajiang Zhou with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Dajiang Zhou more than expected).

Fields of papers citing papers by Dajiang Zhou

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Dajiang Zhou. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Dajiang Zhou. The network helps show where Dajiang Zhou may publish in the future.

Co-authorship network of co-authors of Dajiang Zhou

This figure shows the co-authorship network connecting the top 25 collaborators of Dajiang Zhou. A scholar is included among the top collaborators of Dajiang Zhou based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Dajiang Zhou. Dajiang Zhou is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Zhou, Dajiang, Heming Sun, Jiayi Zhu, et al.. (2016). An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. IEEE Journal of Solid-State Circuits. 52(1). 113–126. 18 indexed citations

Zhou, Dajiang, Heming Sun, Jiayi Zhu, et al.. (2016). 14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. 266–268. 24 indexed citations

Zhou, Jinjia, Dajiang Zhou, Jiayi Zhu, & Satoshi Goto. (2015). A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23(12). 2768–2781. 2 indexed citations

Zhang, Shuping, Jinjia Zhou, Dajiang Zhou, & Satoshi Goto. (2014). A low power 720p motion estimation processor with 3D stacked memory. 4. 1–6. 2 indexed citations

Zhou, Dajiang, et al.. (2014). Reducing power consumption of HEVC codec with lossless reference frame recompression. 20. 2120–2124. 9 indexed citations

Zhou, Dajiang, Jinjia Zhou, Fei Wei, & Satoshi Goto. (2014). Ultra-High-Throughput VLSI Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications. IEEE Transactions on Circuits and Systems for Video Technology. 25(3). 497–507. 50 indexed citations

Zhou, Dajiang, et al.. (2014). VLSI architecture of HEVC intra prediction for 8K UHDTV applications. 1273–1277. 6 indexed citations

He, Gang, Dajiang Zhou, Fei Wei, et al.. (2013). High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22(1). 76–89. 7 indexed citations

Zhou, Dajiang, Gang He, Fei Wei, et al.. (2012). A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC. 154–155. 9 indexed citations

10.

Zhou, Dajiang, Jinjia Zhou, Jiayi Zhu, Peilin Liu, & Satoshi Goto. (2012). A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. 224–226. 17 indexed citations

11.

Zhou, Jinjia, Dajiang Zhou, Gang He, & Satoshi Goto. (2011). A 16–65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications. European Signal Processing Conference. 729–733.

12.

Zhou, Dajiang, Jinjia Zhou, Xun He, et al.. (2011). A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip. IEEE Journal of Solid-State Circuits. 46(4). 777–788. 47 indexed citations

13.

He, Gang, et al.. (2011). A 530Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder. IEICE Transactions on Electronics. E94-C(4). 419–427. 1 indexed citations

14.

Zhou, Jinjia, Dajiang Zhou, Gang He, & Satoshi Goto. (2011). Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder. IEICE Transactions on Electronics. E94-C(4). 439–447. 4 indexed citations

15.

Zhou, Dajiang, Jinjia Zhou, Xun He, et al.. (2010). A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip. 171–172. 17 indexed citations

16.

He, Xun, Dajiang Zhou, Jinjia Zhou, & Satoshi Goto. (2010). High Profile Intra Prediction Architecture for UHD H.264 Decoder. 3(0). 303–313. 1 indexed citations

17.

He, Gang, Dajiang Zhou, Jinjia Zhou, & Satoshi Goto. (2010). Intra prediction architecture for H.264/AVC QFHD encoder. 19. 450–453. 4 indexed citations

18.

He, Xun, Dajiang Zhou, Jinjia Zhou, & Satoshi Goto. (2009). A new architecture for high performance intra prediction in H.264 decoder. 15. 41–44. 1 indexed citations

19.

Zhou, Dajiang, Jinjia Zhou, Jiayi Zhu, & Satoshi Goto. (2009). A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. E92-A(12). 3203–3210. 11 indexed citations

20.

He, Xun, Dajiang Zhou, Jinjia Zhou, & Satoshi Goto. (2009). High profile intra prediction architecture for H.264. 15. 57–60. 2 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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