S. Mutoh

Evaluating Run-Time Techniques for Leakage Power Reduction

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Networks on chips: a new SoC paradigm

I/sub DDQ/ testing for deep-submicron ICs: challenges and solutions

Design and optimization of dual-threshold circuits for low-voltage low-power applications

V/sub TH/-hopping scheme to reduce subthreshold leakage for low-power processors

System-level power optimization

A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits