D. Murray

Device Requirements for Optical Interconnects to Silicon Chips

The worst-case execution-time problem—overview of methods and survey of tools

Latency reduction in optical interconnects using short optical pulses

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

DRG-cache

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

A dynamic voltage scaled microprocessor system

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Path clustering in software timing analysis

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

The benefits of ultrashort optical pulses in optically interconnected systems

A CAM with mixed serial-parallel comparison for use in low energy caches

An adaptive serial-parallel CAM architecture for low-power cache blocks

Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey

A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor