Standout Papers

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS 2008 2026 2014 2020 273
  1. An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS (2008)
    Sriram Vangal, Jason Howard et al. IEEE Journal of Solid-State Circuits

Immediate Impact

1 from Science/Nature 41 standout
Sub-graph 1 of 14

Citing Papers

Terahertz Communications and Sensing for 6G and Beyond: A Comprehensive Review
2024 Standout
Roadmapping the next generation of silicon photonics
2024 Standout
2 intermediate papers

Works of Clark Roberts being referenced

A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS
2014
A Scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS
2013

Author Peers

Author Last Decade Papers Cites
Clark Roberts 190 246 246 4 376
Tiju Jacob 244 224 301 3 374
Christopher Mineo 105 409 165 7 455
Ambarish Mukund Sule 106 344 150 4 390
Burkhard Steinmacher-Burow 182 103 261 7 362
P. Wielage 320 167 373 12 429
J. Kahle 250 156 219 2 418
Mohammad Tabbara 68 58 171 5 372
Nathaniel Pinckney 99 306 67 14 343
D.N. Jayasimha 190 246 370 15 453
Evgeny Bolotin 259 123 310 10 348

All Works

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Rankless by CCL
2026