Christopher Healy

Processor Pipelines and Static Worst-Case Execution Time Analysis

Modeling Out-of-Order Processors for Software Timing Analysis

What’s on the syllabus? An analysis of assessment criteria in first year courses across US and Spanish universities

The worst-case execution-time problem—overview of methods and survey of tools

Hybrid Cache Analysis in Running Time Verification of Embedded Software

Timing Analysis for Instruction Caches

A Modular Tool Architecture for Worst-Case ExecutionTime Analysis

Modeling Control Speculation for Timing Analysis

Timing Analysis for Data and Wrap-Around Fill Caches

Clustered Worst-Case Execution-Time Calculation

A review of feedback models and typologies: Towards an integrative model of feedback elements

Path clustering in software timing analysis

Estimating the Worst-Case Energy Consumption of Embedded Software

The influence of processor architecture on the design and the results of WCET tools

Supporting Timing Analysis by Automatic Bounding of Loop Iterations

Where a is Ordinary: The Evolution of American College and University Grading, 1940-2009

Automatic detection and exploitation of branch constraints for timing analysis

Bounding pipeline and instruction cache performance

Parametric Timing Analysis